4027 Dual JK Flip Flop with Set and Clear

The CD4027 is a CMOS based high-speed, high voltage Dual JK Flip-Flop IC. The Flip-flop could operate at a speed of 16MHz at high voltages up to 15V with a low noise margin of ~ 2.5V.

Features

• Dual JK Flip Flop Package IC
• Operating Speed: 16MHz
• Operating Voltage: 5V, 10V, 15V
• Maximum Operating Voltage: 20V
• Input Rise/Fall time at 5V: 45us
• Minimum High-Level Input Voltage: 2 V
• Maximum Low-Level Input Voltage: 0.8 V
• Available in 14-pin PDIP, GDIP, PDSO packages
• CD4027BMS is a single monolithic chip integrated circuit.
• It contains two identical complementary-symmetry J-K master-slave flip-flops.
• Inputs of each flip-flop: – J, K, Set, Reset, and Clock input signals.
• The output of each flip-flop: – Buffered Q and Q signals.
• This input-output arrangement provides for compatible operation with the CD4013B dual D type flip-flop.
• The CD4027BMS performs: – control, register, and toggle functions.

Pin Configuration

Applications

• Shift Registers
• Memory/Control Registers
• EEPROM circuits
• Latching devices

Pin Description